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參數(shù)資料
| 型號： | MK2049-10SITRLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 185K |
| 代理商： | MK2049-10SITRLF |
Communications Clock PLL
MDS 2049-10 E
9
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-10
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2
are sensitive to noise pickup. In applications that are
especially sensitive to noise, such as SONET or G-Bit
ethernet transceivers, some or all of the following
crystal shielding techniques may be considered. This is
especially important when the MK2049-10 is placed
near high speed logic or signal traces, and when the
VCXO loop bandwidth is below 10 Hz.
1) The metal layer underneath the crystal section
should be the ground layer. Remove all other layers
that are above. This ground layer will help shield the
crystal circuit from other system noise sources. As an
alternative, all layers underneath the crystal can be
removed, however this is not recommended if there are
adjacent PCBs that can induce noise into the
unshielded crystal circuit.
2) Add a through-hole for the optional third lead offered
by the crystal manufacturer (case ground). The
requirement for this third lead can be made at
prototype evaluation. The crystal is less sensitive to
system noise interference when the case is grounded.
3) Add a ground trace around the crystal circuit to
shield from other active traces on the component layer.
The external crystal is particularly sensitive to other
system clock sources that are at or near the crystal
frequency since it will try to lock to the interfering clock
source. This can adversely affect crystal operation if
the VCXO loop bandwidth is low, such as under 10 Hz.
It is good practice in general to keep the crystal away
from other clock sources.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
Optimization of Crystal Load
Capacitors
The concept behind the crystal load capacitors is
introduced on page 8. To determine the need for and
value of these capacitors, you will need a PC board of
your final layout, a frequency counter capable of less
than 1 ppm resolution and accuracy, two power
supplies, and some samples of the crystals which you
plan to use in production, along with measured initial
accuracy for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049-10 to 5V. Connect pin
5 to the second power supply. Adjust the voltage on pin
5 to 0V. Measure and record the frequency of the CLK
output.
2. Adjust the voltage on pin 5 to 5V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±15 ppm, no
adjustment is needed. If the centering error is more
than 15 ppm negative, the PC board has too much
stray capacitance and will need to be redone with a
new layout to reduce stray capacitance. (The crystal
may be re-specified to a lower load capacitance
instead. Contact ICS MicroClock for details.) If the
centering error is more than 15 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (less than ±15ppm).
Error
10
6
x
f
5V
f
tet
arg
–
()
f
0V
f
tet
arg
–
()
+
2
f
tet
arg
×
--------------------------------------------------------------------------
error
xtal
–
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-10SI | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-10SI | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-10SILF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-10SITR | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-10SITRLF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SAILF | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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