參數(shù)資料
型號: MK2049-10SILF
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20
封裝: 0.300 INCH, SOIC-20
文件頁數(shù): 7/13頁
文件大?。?/td> 185K
代理商: MK2049-10SILF
Communications Clock PLL
MDS 2049-10 E
3
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-10
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FS1
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
2
X2
-
Crystal Output. Connect this pin to the external reference crystal.
3
X1
-
Crystal Input. Connect this pin to the external reference crystal.
4
VDD
Power
Power Supply. Connect to +5V.
5
VDD
Power
Power Supply. Connect to +5V.
6
VDD
Power
Power Supply. Connect to +5V.
7
GND
Power
Ground.
8
CLK2
Output
Clock output, frequency determined by status of FS3:0 per table on
page 2.
9
CLK1
Output
Clock output, frequency determined by status of FS3:0 per table on
page 2.
10
8k
Output
8.000kHz Clock Output, applicable modes only, refer to table on page 2.
11
FS2
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
12
FS3
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
13
ICLK
Input
Input Clock Connection.
14
GND
Power
Ground.
15
VDD
Power
Power Supply. Connect to +5V.
16
CAP1
-
Loop Filter Connection. Refer to Block Diagram on page 1.
17
GND
Power
Ground.
18
CAP2
-
Loop Filter Connection. Refer to Block Diagram on page 1.
19
NC
-
No internal connection. This pin should be connected to ground to
minimize noise coupling into pin CAP2.
20
FS0
Input
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
相關(guān)PDF資料
PDF描述
MK2049-10SITR 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20
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