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參數(shù)資料
| 型號： | MK1621-01STR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 27 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 36K |
| 代理商： | MK1621-01STR |
MK1621
Audio Clock Source
MDS 1621C A
3
Revision 072597
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
I C R O
C LOC K
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-12mA
VDD-0.4
V
Output Low Voltage, VOL
IOL=12mA
0.4
V
Operating Supply Current, IDD, 5.0V
No Load
23
mA
Operating Supply Current, IDD, 3.3V
No Load
13
mA
Power Down Supply Current, IDDPD, 5V
No Load
7
A
Short Circuit Current
Each output
±50
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency
24.576
MHz
Input Crystal Accuracy
±30
ppm
Frequency Error, 27 MHz
6
ppm
Frequency Error, 13.5 MHz
6
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
45
50
55
%
Maximum Absolute Jitter, short term
200
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The MK1621 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND on pins 3 and 5, as close to the MK1621
as possible. A series termination resistor of 33
may be used for each clock output. If a clock input is not
used, the 24.576 MHz crystal must be connected as close to the chip as possible; if the crystal has a load
capacitance of 18pF or less, no external capacitors are needed for the crystal. If exact tuning is required for
crystals with load capacitance above 18 pF, crystal capacitors should be connected from pins X1 to ground
and X2 to ground. The value (in pF) of these crystal capacitors should be = (CL-18)*2, where CL is the
crystal load capacitance in pF. So for a crystal with 20pF load capacitance, the crystal capacitors should be
4pF each.
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