參數(shù)資料
型號: MK1493-03BGILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, TSSOP-48
文件頁數(shù): 15/19頁
文件大?。?/td> 440K
代理商: MK1493-03BGILF
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT PCI CLOCK GENERATOR
5
MK1493-03B
REV H 051310
How to Read:
Controller (host) will send a start bit
Controller (host) sends the write address D2
(H)
IDT clock will acknowledge
Controller (host) sends the beginning Byte location = N
IDT clock will acknowledge
Controller (host) will send a repeat start bit
Controller (host) sends the read address Byte D3
(H)
IDT clock will acknowledge
IDT clock will send the data Byte count = X
IDT clock sends Byte N
IDT clock sends Byte N+X-1
Controller (host) will need to acknowledge each Byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
SMBus Table 3: Read-Back Register
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
T
starT bit
Slave Address
D2 (H)
WR
=0
ACK
Beginning Loc = N
ACK
RT
repeat
starT
Slave Address
D2 (H)
RD
=1
ACK
Data Byte Count=X
ACK
X
B
Y
T
E
S
Beginning Byte N
ACK
O
Byte N + X - 1
N
NAK
PstoP bit
Byte 0
Pin #
Name
Control
Function
Type
0
1
Power
UP State
Bit 7
-
RESERVED
0
Bit 6
-
FS vs. SMBus
prog
HW/SW select
RW
HW
SW
0
Bit 5
-
RESERVED
0
Bit 4
-
Frequency
Selection
See Frequency table 4
0
Bit 3
-
0
Bit 2
-
0
Bit 1
-
0
Bit 0
-
0
相關(guān)PDF資料
PDF描述
MK1493-03BGLF 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
MK1493-03BGILFTR 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
MK1705ATR 167 MHz, VIDEO CLOCK GENERATOR, PDSO8
MK1705ALF 167 MHz, VIDEO CLOCK GENERATOR, PDSO8
MK1705A 167 MHz, VIDEO CLOCK GENERATOR, PDSO8
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