
MK1492-02
Intel Mobile/SDRAM Clock Source
MDS1492-02E
1
Revision 2028
Printed 2/2/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
Block Diagram
Description
Features
The MK1492-02 is a low cost, low jitter, high
performance clock synthesizer for Intel’s 430TX
and 440BX chipsets for Pentium and Pentium
II Processor based computer applications. Using
patented analog Phase-Locked Loop (PLL)
techniques, the device accepts a 14.318 MHz
crystal input to produce multiple output clocks
up to 75 MHz. It provides selectable Host and
Host/2 PCI local bus clocks and a selectable
24/48 MHz clock for Super I/O or Universal
Serial Bus (USB). The device has up to eight
Host output clocks, and includes a serial port for
controlling the output clocks.
The chip has three different power down modes
to reduce power consumption.
I2C Serial Port for ACPI support
Packaged in 28 pin, 150 mil wide SSOP
Provides all critical timing for Intel mobile chipsets
Separate VDD and auto adjust for Host 1,2
supports 3.3 V or 2.5V processors
48MHz USB or 24MHz SIO support
Single pin CPU(Host) slowdown to 33.3MHz option
Multiple power down modes
Low EMI Enable pin reduces EMI radiation on
HOST and PCI clocks (patented)
Selectable PCIF on up to 3 outputs
Crystal
Oscillator
VDD
GND
HOST/PCI
Clocks
CPU Frequency Select
PCISTP#
14.31818 MHz
crystal
Output
Buffers
Output
Buffer
Fixed
Clock
Output
Buffers
XI
XO
CPUS#
24M/48M Select
Host/2
14.318 MHz or
24.000 MHz or
PCI
HOST 5:8
PCI 1:4
Low EMI Enable
OE (all outputs)
Output
Buffer
14.318 MHz
24 MHz or
48 MHz
Output
Buffer
CPU Slow/Stop Select
PCI Free Run Enable
2
4
HOST1,2
SDATA
SDCLK
14.3/24/PCI Select
MUX
Output
Buffers
VDDHOST1, 2
HOST3, 4
Output
Buffers
2
VDDHOST3, 4
DS
I2C
Control