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參數(shù)資料
| 型號(hào)： | MK1422STR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 33.868 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 43K |
| 代理商： | MK1422STR |
MK1422
OPL3/4+Codec Portable Clock Source
MDS 1422 B
2
Revision 080698
Printed 11/15/00
Integrated Circuit Systems525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
Number
Name
Type
Description
1
X1/ICLK
I
Crystal Connection. Connect to a 14.318 MHz crystal or clock.
2
VDD
P
Connect to +5V.
3
GND
P
Connect to ground.
4
16.9M
O
16.9344 MHz clock output for stereo codec.
5
24.6M
O
24.576 MHz clock output for stereo codec.
6
33.9M
O
33.868 MHz clock output for OPL4.
7
PD
I
Power Down. Shuts off entire chip when low. All clock outputs stop low.
8
X2
O
Crystal Connection to a 14.318 MHz crystal, or leave unconnected for clock input.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
1
8
2
3
4
7
6
5
X1/ICLK
VDD
GND
16.9M
X2
PD
33.9M
24.6M
14.318 MHz in
Pin 1
33
(optional)
2
3
5
6
7
0.1F
16.9MHz out
24.6MHz out
G
V
33
(optional)
Suggested Layout
4
8
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel
resonant 14.318 MHz, 16pF load, crystal is recommended. Load capacitor values near these are acceptable,
as is a series resonant crystal, but either will result in frequencies which are further off of the target
frequency. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of 0.1F
should be connected between VDD and GND, and 33
terminating resistors may be used on the clock
outputs.
33
(optional)
33.9MHz
out
PD
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