Figure 26. I
參數(shù)資料
型號: MK10DN512ZVLL10R
廠商: Freescale Semiconductor
文件頁數(shù): 54/68頁
文件大小: 0K
描述: IC ARM CORTEX MCU 512KB 100LQFP
標準包裝: 1,000
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 70
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 29x16b,D/A 1x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 帶卷 (TR)
S15
S13
S15
S17
S18
S15
S16
S14
S16
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 26. I2S timing — slave modes
Table 46. I2S master mode timing (full voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
2 x tSYS
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_BCLK cycle time
5 x tSYS
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
15
ns
S6
I2S_BCLK to I2S_FS output invalid
-4.3
ns
S7
I2S_BCLK to I2S_TXD valid
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-4.6
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
23.9
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
ns
Table 47. I2S slave mode timing (full voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_BCLK cycle time (input)
8 x tSYS
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
ns
S14
I2S_FS input hold after I2S_BCLK
3.5
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
28.6
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
ns
S17
I2S_RXD setup before I2S_BCLK
10
ns
S18
I2S_RXD hold after I2S_BCLK
2
ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
58
Freescale Semiconductor, Inc.
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