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參數(shù)資料
| 型號： | MIP7965-750F17I |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 750 MHz, MICROPROCESSOR, CQFP208 |
| 封裝： | 1.120 X 1.120 INCH, CERAMIC, QFP-208 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MIP7965-750F17I |
9
SCD7965 Rev H 10/01/10
Aeroflex Plainview
AC CHARACTERISTICS
CAPACITIVE LOAD DERATION
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
Mode
CLD
Load Derate
-
2
ns/25pF
LVTTL
CLOCK PARAMETERS
PARAMETER
SYMBOL
TEST CONDITIONS
BUS SPEED
UNITS
LVTTL
MIN
MAX
SysClock High
tSCHigh
Transition < 2ns
3
-
ns
SysClock Low
tSCLow
Transition < 2ns
3
-
ns
SysClock Frequency1
33.3
100
MHz
SysClock Period
tSCP
10
30
ns
Clock Jitter for SysClock
tJitterIn
-±150
ps
SysClock Rise Time
tSCRise
-2
ns
SysClock Fall Time
tSCFall
-2
ns
ModeClock Period
tModeCKP
-
256
tSCP
JTAG Clock Period
tJTAGCKP
4-
tSCP
Notes:
1. Operation of the MIP7965 is only guaranteed with the Phase Loop enabled.
SYSTEM INTERFACE PARAMETERS
PARAMETER1
SYM
TEST CONDITIONS
BUS SPEED
UNITS
LVTTL I/O
MIN
MAX
Data Output2
tDO
LVTTL (VccIO = 3.3V): mode[15:14] = 10 (fastest)4,5,6
0.75
4.5
ns
LVTTL (VccIO = 3.3V): mode[15:14] = 01 (slowest)4,5,6
0.75
5.5
ns
Data Setup3
tDS
5
tRISE = See above table
2.5
-
ns
Data Hold3
tDH
tFALL= See above table
1.0
-
ns
Notes
1. In LVTTL mode, timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O, and from 0.48 x VccIO
of clock to 0.48 x VccIO of signal for 2.5V I/O.
2. Capacitive load for all LVTTL maximum output timings is 50 pF. Minimum output timings are for theoretical no load conditions.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode [15:14] = 10 is tested and guaranteed.
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