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    參數(shù)資料
    

    


    


    
型號(hào)：
MC68HC705RC16P

    

    
廠商：
MOTOROLA INC

    

    
元件分類：
微控制器/微處理器

    

    
英文描述：
8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28

    

    
封裝：
PLASTIC, DIP-28

    

    
文件頁數(shù)：
117/120頁

    

    
文件大小：
547K

    

    
代理商：
MC68HC705RC16P


    

    

    

	
    
    
    

    
    
	
    NON-DISCLOSURE
    AGREEMENT
    REQUIRED
    Instruction Set
    General Release Specification
    MC68HC705RC16 — Rev. 3.0
    96
    Instruction Set
    MOTOROLA
    11.4.3 Jump/Branch Instructions
    Jump instructions allow the CPU to interrupt the normal sequence of the
    program counter. The unconditional jump instruction (JMP) and the
    jump-to-subroutine instruction (JSR) have no register operand. Branch
    instructions allow the CPU to interrupt the normal sequence of the
    program counter when a test condition is met. If the test condition is not
    met, the branch is not performed.
    The BRCLR and BRSET instructions cause a branch based on the state
    of any readable bit in the first 256 memory locations. These 3-byte
    instructions use a combination of direct addressing and relative
    addressing. The direct address of the byte to be tested is in the byte
    following the opcode. The third byte is the signed offset byte. The CPU
    finds the effective branch destination by adding the third byte to the
    program counter if the specified bit tests true. The bit to be tested and its
    condition (set or clear) is part of the opcode. The span of branching is
    from –128 to +127 from the address of the next location after the branch
    instruction. The CPU also transfers the tested bit to the carry/borrow bit
    of the condition code register.
    
    
    
    
    
    


    


    

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