參數(shù)資料
型號: MIC2583R-MBQS
廠商: MICREL INC
元件分類: 電源管理
英文描述: Single Channel Hot Swap Controllers
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝: QSOP-16
文件頁數(shù): 16/22頁
文件大?。?/td> 190K
代理商: MIC2583R-MBQS
MIC2582/MIC2583
Micrel
MIC2582/MIC2583
16
April 2003
control from the processor or other signal controller to shut off
the output of the MIC2582/83. R4 pulls the GATE of Q2 to V
IN
and the ON pin is held low until the connectors are fully mated.
Once the connectors fully mate, a logic LOW at the /ON_OFF
signal turns Q2 off and allows the ON pin to pull up above its
threshold and initiate a start-up cycle. Applying a logic HIGH
at the /ON_OFF signal will turn Q2 on and short the ON pin
of the MIC2582/83 to ground which turns off the GATE output
charge pump.
Higher UVLO Setting
Once a PCB is inserted into a backplane (power supply), the
internal UVLO circuit of the MIC2582/83 holds the GATE
output charge pump off until V
CC
exceeds 2.2V. If VCC falls
below 2.1V, the UVLO circuit pulls the GATE output to ground
and clears the overvoltage and/or current limit faults. For a
higher UVLO threshold, the circuit in Figure 7 can be used to
delay the output MOSFET from switching on until the desired
input voltage is achieved. The circuit allows the charge pump
to remain off until V
IN
exceeds
1
R1
R2
1.24V
+
. The GATE
drive output will be shut down when V
IN
falls below
R1
R2
UVLO threshold is set at approximately 9.5V and the falling
UVLO threshold is established as 9.1V. The circuit consists
of an external resistor divider at the ON pin that keeps the
GATE output charge pump off until the voltage at the ON pin
exceeds its threshold (V
ON
) and after the start-up timer
elapses.
1
1.19V
+
. In the example circuit (Figure 7), the rising
5V Switch with 3.3V Supply Generation
The MIC2582/83 can be configured to switch a primary
supply while generating a secondary regulated voltage rail.
The circuit in Figure 8 enables the MIC2582 to switch a 5V
supply while also providing a 3.3V low dropout regulated
supply with only a few added external components. Upon
enabling the MIC2582, the GATE output voltage increases
and thus the 3.3V supply also begins to ramp. As the 3.3V
output supply crosses 3.3V, the FB pin threshold is also
exceeded which triggers the power-on reset comparator. The
/POR pin goes HIGH, turning on transistor Q3 which lowers
the voltage on the gate of MOSFET Q2. The result is a
regulated 3.3V supply with the gate feedback loop of Q2
compensated by capacitor C3 and resistors R4 and R5. For
MOSFET Q2, special consideration must be given to the
power dissipation capability of the selected MOSFET as 1.5V
to 2V will drop across the device during normal operation in
this application. Therefore, the device is susceptible to over-
heating dependent upon the current requirements for the
regulated output. In this example, the power dissipated by Q2
is approximately
1W. However, a substantial amount of
power will be generated with higher current requirements
and/or conditions. As a general guideline, expect the ambient
temperature within the power supply box to exceed the
maximum operating ambient temperature of the system
environment by approximately 20
°
C. Given the MOSFET
s
R
θ
(J-A)
and the expected power dissipated by the MOSFET,
an approximation for the junction temperature at which the
device will operate is obtained as follows:
T
J
= (P
D
x R
θ
(J-A)
) + T
A
'
where T
A
'=T
A(MAX OPERATING)
+ 20
°
C. As a precaution, the
implementation of additional copper heat sinking is highly
recommended for the area under/around the MOSFET.
For additional information on MOSFET thermal consider-
ations, please see MOSFET Selection text and subsequent
sections.
(10)
SENSE
VCC
ON
FB
GATE
GND
Undervoltage Lockout Threshold (rising) = 9.5V
Undervoltage Lockout Threshold (falling) = 9.1V
Undervoltage (Output) = 11.4V
Additional pins omitted for clarity.
Q1
IRF7822
(SO-8)
R3
10
R5
16.2k
1%
R1
332k
1%
R2
49.9k
1%
MIC2582
C1
1
μ
F
D1
(18V)
C2
0.01
μ
F
C
220
μ
F
R4
133k
1%
V
12V@4A
V
IN
12V
4
8
7
5
2
6
R
0.010
5%
1
2
3
4
Figure 7. Higher UVLO Setting
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