參數(shù)資料
型號(hào): MIC2555-1YML TR
廠商: Micrel Inc
文件頁(yè)數(shù): 8/29頁(yè)
文件大?。?/td> 0K
描述: IC TXRX OTG USB BUS UNIV 24MLF
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/0
規(guī)程: USB 2.0
電源電壓: 3 V ~ 4.5 V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應(yīng)商設(shè)備封裝: 24-MLF?(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1113 (CN2011-ZH PDF)
其它名稱: 576-1088-6
Micrel, Inc.
MIC2555
December 2006
16
M9999-121406
USB Receive Operation
Inputs
Outputs
USB Mode
Suspend
D+
D-
DAT_VP_RX
SE0_VM_TX
RCV
0
undefined
1
n/a
0
1
0
1
0
n/a
0
1
0
n/a
0
1
undefined
0
n/a
1
0
1
n/a
1
0
1
0
n/a
1
0
1
0
n/a
DAT-SE0
1
0
n/a
0
undefined
0
1
0
1
0
1
0
1
0
1
0
1
undefined
1
0
n/a
1
0
1
0
n/a
1
0
1
0
1
n/a
VP-VM
1
n/a
If the transceiver is in the DAT-SE0 mode, and the
suspend bit has not been set, then the DAT_VP_RX pin
always follows the output of the differential receiver
during receive operation. The DAT_SE0 pin is not gated
by the outputs of the single ended receivers. In the VP-
VM mode, the RVC pin always follows the output of the
differential receiver. The RVC pin is not gated by the
outputs of the singled ended receivers.
UART mode:
uart_en = 1
suspend
DAT_VP
SE0_VM
D+
D-
0
SE_DP
TX data
RX data
SE0_VM
1
Z
Z = Tri-State
Single-Ended Receivers
The Single Ended Receivers detect the logic levels on
the D+ and D- lines, and provide this information to the
Single Ended Decoder.
Single-Ended Decoder
Behavior of the Single-Ended Decoder is dependent
upon the power mode of the transceiver. If transceiver is
in the Suspend power mode, and dat_se0 = 1 (DAT-SE0
mode), then the DAT_VP_RX pin will reflect the output
of the D+ single ended receiver. This is necessary so
that a controller connected to the transceiver can detect
data pulsing while the transceiver is in suspended mode.
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