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參數(shù)資料
| 型號(hào)： | MHW1810 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LDMOS RF Power Transistors.(LDMOS射頻功率管) |
| 中文描述： | LDMOS射頻功率晶體管。（LDMOS的射頻功率管） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 50K |
| 代理商： | MHW1810 |
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Motorola, Inc. 1998
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Prepared by: Julie Duclercq and Olivier Lembeye
Motorola Semiconductor Products Sector
Toulouse, France
INTRODUCTION
The performances of RF power amplifiers for base station
transceivers results in a tradeoff between linearity, efficiency
and gain. This tradeoff leads to an optimum quiescent
current. But the following parameters modify this bias point:
temperature range (commonly –40
°
C/+85
°
C), supply voltage
and bias voltage variations (commonly +/–5%) and
manufacturing spread. The purpose of this paper is to
present a new biasing circuit which minimizes quiescent
current variations suitable for LDMOS RF power transistors.
STANDARD BIASING CIRCUIT
A standard biasing circuit commonly used for Class AB
transistors is shown in Figure 1.
Figure 1. Standard Biasing Circuit
V
BIAS
V
SUPPLY
I
Q
V
G
V
D
R1
R2
For each LDMOS transistor, it is necessary to adjust the R1
and R2 values in order to set the quiescent current as
specified at ambient temperature. Laser–trimmable resistors
can be used in mass production for that purpose.
The addition of a diode in series with the two resistors allows
for reduction of the quiescent current variation over
temperature. We have:
R2
R1
R2
V
G
=
R1
R1
R2
V
D
(Equation 1)
=
R1
R1
R2
(Equation 2)
dVd
V
BIAS
+
then,
R2
R1
R2
dVg =
R1
R1
R2
dVd (Equation 1.bis)
dV
BIAS
+
when dV
BIAS
= 0, we have:
dVg
Considering variations due to temperature, the coefficient
dVd
dT
the quiescent current. For class AB biasing, this coefficient is
around –2mV/
°
C. For full thermal tracking, more than one
diode may be required because of the ratio
to apply to the LDMOS is related to the bias point, i.e.,
R1
R1
R2
in
equation 2.
However, this standard biasing circuit presents two major
limitations:
Limitation 1:the manufacturing spread of threshold voltage
leads to a different
R1
R2
the dice is not compensated for in the same way. A die with a
high threshold voltage requires a ratio
R1
ratio for each die. Therefore, all
R1
R1
R2
lower than for
a die with a low threshold voltage. Subsequently, the thermal
compensation is lower for a die with a high threshold voltage
than for a die with a low threshold voltage. This results in
quiescent current over or under compensation versus
temperature.
Limitation 2:equation 1 shows that Bias voltage variations
induce proportional gate voltage variations weighed by a ratio
R2
R1
R2
quiescent current variations via the die transconductance.
As a result, we have designed a new biasing circuit to cope
with those limitations.
. Thus these gate voltage variations lead to
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SEMICONDUCTOR APPLICATION NOTE
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