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參數(shù)資料
| 型號(hào)： | MHVIC910HR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 衰減器 |
| 英文描述： | 921 MHz − 960 MHz SiFET RF Integrated Power Amplifier |
| 中文描述： | 921 MHz - 960 MHz RF/MICROWAVE NARROW BAND HIGH POWER AMPLIFIER |
| 封裝： | PLASTIC, CASE 978-03, FP-16 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | MHVIC910HR2 |
Will be replaced by MHVIC910HNR2 end of Q205. N suffix indicates 260
°
C reflow
capable. The PFP
16 package has had lead
free terminations from its initial release.
MHVIC910HR2
1
RF Device Data
Freescale Semiconductor
921 MHz
960 MHz SiFET
RF Integrated Power Amplifier
The MHVIC910HR2 integrated circuit is designed for GSM base stations,
uses Freescale’s newest High Voltage (26 Volts) LDMOS IC technology, and
contains a three
stage amplifier. Target applications include macrocell (driver
function) and microcell base stations (final stage). The device is in a PFP
16
Power Flat Pack package which gives excellent thermal performances through
a solderable backside contact.
Typical GSM Performance @ Full Frequency Band
(921
960 MHz), 26 Volts
Output Power — 40 dBm (CW) @ P1dB
Power Gain — 39 dB @ P1dB
Efficiency — 48% @ P1dB
On
Chip Matching (50 Ohm Input, DC Blocked, >5 Ohm Output)
Integrated ESD Protection
Usable Frequency Range — 921 to 960 MHz
In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain Supply Voltage
V
DD
28
Vdc
Gate Supply Voltage
V
GS
6
Vdc
RF Input Power
P
in
5
dBm
Case Operating Temperature
T
C
30 to + 85
°
C
Storage Temperature Range
T
stg
65 to + 150
°
C
Operating Channel Temperature
T
ch
150
°
C
Table 2. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
θ
JC
2.9
°
C/W
MHVIC910HR2
Rev. 5, 1/2005
Freescale Semiconductor
Technical Data
960 MHz, 10 W, 26 V
GSM CELLULAR
RF LDMOS INTEGRATED CIRCUIT
CASE 978
03
PFP
16
MHVIC910HR2
16
1
Figure 1. Functional Block Diagram
V
D1
V
D2
Figure 2. Pin Connections
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
(Top View)
9
N.C.
V
D2
V
D1
GND
RF
in
V
GATE1
V
GATE2
V
GATE3
N.C.
V
D3
/RF
out
V
D3
/RF
out
V
D3
/RF
out
V
D3
/RF
out
V
D3
/RF
out
N.C.
N.C.
V
GATE3
V
D3
RF
out
RF
in
V
GATE1
V
GATE2
Note: Exposed backside flag is source
terminal for transistors.
Freescale Semiconductor, Inc., 2005. All rights reserved.
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