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參數(shù)資料
| 型號： | MH64D64AKQH-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-35 RoHS Compliant: No |
| 中文描述： | 4294967296位（67108864字64位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 362K |
| 代理商： | MH64D64AKQH-75 |
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0418-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
30
Write Interrupted by Write (BL=8)
Command
A0-9,11-12
A10
BA0,1
WRITE
Yi
0
00
WRITE
Yk
0
10
WRITE
Yj
0
00
WRITE
Yl
0
00
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
DQ
Dai1
Daj1
Daj3
Dak1
Dak3
Dak5
Dal1
DQS
Dal2 Dal3
Dal5
Dal6 Dal7
Dal4
Dal0
Dak4
Dak2
Dak0
Dai0
Daj0
Daj2
/CLK
CLK
Command
A0-9,11-12
A10
BA0,1
DQ
WRITE
Yi
0
00
READ
Yj
0
00
Dai0
Dai1
Qaj0 Qaj1 Qaj2 Qaj3
QS
Qaj4 Qaj5 Qaj6 Qaj7
DM
tWTR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH88422BD-1 | Data Access Arrangement Preliminary Information |
| MH88422 | Line Interface Circuit Preliminary Information |
| MH88422-1 | Data Access Arrangement Preliminary Information |
| MH88422-2 | Data Access Arrangement Preliminary Information |
| MH88422-3 | Data Access Arrangement Preliminary Information |
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| MH64D72KLG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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