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| 型號： | MFRC53101T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ISO-IEC 14443 reader IC |
| 封裝： | MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html< |
| 文件頁數(shù)： | 43/116頁 |
| 文件大?。?/td> | 862K |
| 代理商： | MFRC53101T |
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MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
43 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
10.3 Register overview
Table 37.
Sub
address
(Hex)
Page 0: Command and status
00h
Page
01h
Command
02h
FIFOData
03h
PrimaryStatus
04h
FIFOLength
05h
SecondaryStatus
06h
InterruptEn
07h
InterruptRq
Page 1: Control and status
08h
Page
09h
Control
0Ah
ErrorFlag
0Bh
CollPos
0Ch
TimerValue
MFRC531 register overview
Register name
Function
Refer to
selects the page register
starts and stops command execution
input and output for the 64-byte FIFO buffer
receiver, transmitter and FIFO buffer status flags
number of bytes buffered in the FIFO buffer
secondary status flags
enable and disable interrupt request control bits
interrupt request flags
Table 39 on page 48
Table 41 on page 48
Table 43 on page 49
Table 45 on page 49
Table 47 on page 50
Table 49 on page 51
Table 51 on page 51
Table 53 on page 52
selects the page register
control flags for timer unit, power saving etc
show the error status of the last command executed
bit position of the first bit-collision detected on the RF interface
value of the timer
Table 39 on page 48
Table 55 on page 53
Table 57 on page 53
Table 59 on page 54
Table 61 on page 55
0Dh
0Eh
0Fh
Page 2: Transmitter and coder control
10h
Page
11h
TxControl
12h
CwConductance
13h
ModConductance
14h
CoderControl
15h
ModWidth
16h
ModWidthSOF
17h
TypeBFraming
Page 3: Receiver and decoder control
18
Page
19
RxControl1
1A
DecoderControl
1B
BitPhase
1C
RxThreshold
1D
BPSKDemControl
1Eh
RxControl2
1Fh
ClockQControl
CRCResultLSB
CRCResultMSB
BitFraming
LSB of the CRC coprocessor register
MSB of the CRC coprocessor register
adjustments for bit oriented frames
Table 63 on page 55
Table 65 on page 55
Table 67 on page 56
selects the page register
controls the operation of the antenna driver pins TX1 and TX2
selects the conductance of the antenna driver pins TX1 and TX2
Table 71 on page 58
defines the driver output conductance
sets the clock frequency and the encoding
selects the modulation pulse width
selects the SOF pulse-width modulation
defines the framing for ISO/IEC 14443 B communication
Table 39 on page 48
Table 69 on page 57
Table 73 on page 58
Table 75 on page 59
Table 77 on page 59
Table 79 on page 59
Table 80 on page 60
selects the page register
controls receiver behavior
controls decoder behavior
selects the bit-phase between transmitter and receiver clock
selects thresholds for the bit decoder
controls BPSK receiver behavior
controls decoder and defines the receiver input source
clock control for the 90
°
phase-shifted Q-channel clock
Table 39 on page 48
Table 82 on page 61
Table 84 on page 62
Table 86 on page 62
Table 88 on page 63
Table 90 on page 63
Table 92 on page 64
Table 94 on page 64
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