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| 型號： | MFR4200MAE40R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 PITCH, LEAD FREE, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 86/260頁 |
| 文件大小： | 1599K |
| 代理商： | MFR4200MAE40R |
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MFR4200 FlexRay Communication Controller
MFR4200 Data Sheet, Rev. 1
176
Freescale Semiconductor
3.5.6.1.2
CC Operations during Reception
The CC receives every frame to a shadow message buffer first, as shown in Figure 3-136.
NOTE
A frame received in slot n and stored in a configured message buffer or FIFO
is accessible to the host, through the CHI, 16 T after the start of slot n+1.
The CC performs a filtering process based on filter configuration. This process takes place every time the
CC receives a semantically valid and syntactically correct frame. In this process, the CC sequentially
compares all the receive message buffers filters to the received ones. The first message buffer matching all
the filtering requirements will be updated with the new frame. The matching message buffer will be
overwritten, if the message buffer was already full (IFLG = 1). If a received frame does not match the
filtering fields of any receive message buffer, it will be compared with the FIFO filters. If a frame matches
the FIFO filtering parameters, it will be stored in the FIFO; otherwise, it will be ignored. The CC ignores
invalid frames and does not store them in buffers.
The received frame will be stored in the first matching receive message buffer. The search engine starts
after the end of the FIFO, or at message buffer 0 (if no FIFO is configured), and searches upwards. Thus,
if there are two receive message buffers matching the received frame, the frame will always be stored in
the buffer with the lower buffer index. The CC does not check which buffer fits the frame best. Thus, if a
message buffer holds a filtering subset of another message buffer, that message buffer (with the filtering
subset) must be located at the lower message buffer index. The application must manage this.
The matching message buffer will not be updated if it is still locked. If the message buffer is locked after
reception, it will be updated as soon as it is unlocked. If the buffer is locked for more than one
communication cycle and, if the frame, which matches that message buffer filtering, is received twice
during this period, the buffer will be updated with the newer frame, as soon as it is unlocked, and a frame
lost error will be raised to the host (see Section 3.2.3.6.3, “CHI Error Register (CHIER)”). The
corresponding IFLG bit (message buffer is full) is set every time the message buffer is updated, and, if
enabled, a receive interrupt is generated.
In the case of locking, when the host may lock one receive message buffer, the CC has two shadow message
buffers per channel to continue frame reception targeted for any receive message buffers including the
locked one.
NOTE
During the filtering process, the CC must check the payload length field of
a received frame before the CC applies message ID filtering. If the payload
length of a received frame is too small to hold the full message ID value, the
CC performs the message ID filtering with the default message ID value
(0x0).
3.5.6.2
Data Collection during Transmit Operation
Some or all of the message buffers can be configured as transmit message buffers via the BUFCSnR
register sets (see Section 3.4.1, “Message Buffer Control, Configuration and Status Register”). The
configuration of transmit message buffers must comply with the buffer configuration procedure and
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