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參數(shù)資料
| 型號(hào)： | MF280C51C-25R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 69/336頁(yè) |
| 文件大?。?/td> | 8801K |
| 代理商： | MF280C51C-25R |
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160
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
This is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the
bus nodes.
19.3.3.4
Phase Segment 1
Phase Segment 1 is used to compensate for edge phase errors.
This segment may be lengthened during re-synchronization.
19.3.3.5
Sample point
The sample point is the point of time at which the bus level is read and interpreted as the value of the respective
bit. Its location is at the end of Phase Segment 1 (between the two Phase Segments).
19.3.3.6
Phase Segment 2
This segment is also used to compensate for edge phase errors.
This segment may be shortened during re-synchronization, but the length has to be at least as long as the Informa-
tion Processing Time (IPT) and may not be more than the length of Phase Segment 1.
19.3.3.7
Information processing time
It is the time required for the logic to determine the bit level of a sampled bit.
The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Seg-
ment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than
the IPT.
19.3.3.8
Bit lengthening
As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to
compensate for oscillator tolerances. If, for example, the transmitter oscillator is slower than the receiver oscillator,
the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to
adjust the sample point and the end of the bit time.
19.3.3.9
Bit shortening
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resyn-
chronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit
N+1 and the end of the bit time.
19.3.3.10
Synchronization jump width
The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump
Width.
This segment may not be longer than Phase Segment 2.
19.3.3.11
Programming the sample point
Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump Width can be pro-
grammed to its maximum. This maximum capacity to shorten or lengthen the bit time decreases the sensitivity to
node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and
maximum bus length.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C52XXX-16SBR | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52EXXX-20P883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52XXX-20SCD | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C32E-36SBD | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-36SB | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MF283C151C-12 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MF283C151C-30 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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