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參數(shù)資料
| 型號(hào)： | MF280C51-36R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 97/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MF280C51-36R |
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73
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the
Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that the FOC0B
bit is implemented as a strobe. Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
The FOC0B bit always reads as zero.
Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny20 and will always read as zero.
Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 69.
Bits 2:0 – CS0[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 11-9.
Clock Select Bit Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is
configured as an output. This feature allows software control of the counting.
11.9.3 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the
counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the
OCR0x Registers.
CS02
CS01
CS00
Description
0
No clock source (Timer/Counter stopped)
0
1
clkI/O/(No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
clkI/O/64 (From prescaler)
1
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
0
External clock source on T0 pin. Clock on falling edge.
1
External clock source on T0 pin. Clock on rising edge.
Bit
76543210
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
00000000
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