參數(shù)資料
型號： MF280C51-30D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 146/176頁
文件大?。?/td> 2962K
代理商： MF280C51-30D
71
2535J–AVR–08/10
ATtiny13
Table 11-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 64
for more details.
Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 66 for more details.
Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
Table 11-5.
Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
Normal port operation, OC0B disconnected.
0
1
Toggle OC0B on Compare Match
1
0
Clear OC0B on Compare Match
1
Set OC0B on Compare Match
Table 11-6.
Compare Output Mode, Fast PWM Mode(1)
COM01
COM00
Description
0
Normal port operation, OC0B disconnected.
01
Reserved
1
0
Clear OC0B on Compare Match, set OC0B at TOP
1
Set OC0B on Compare Match, clear OC0B at TOP
Table 11-7.
Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
Normal port operation, OC0B disconnected.
01
Reserved
10
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
11
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
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