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參數(shù)資料
| 型號： | MF280C31-30D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 74/80頁 |
| 文件大小： | 5152K |
| 代理商： | MF280C31-30D |
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274
XMEGA A [MANUAL]
8077I–AVR–11/2012
Table 24-13. SDRAM column bits.
24.9.3 REFRESH – SDRAM Refresh Period register
Bit 15:10 – Reserved
These bits are unused and reserved for future use.
Bit 9:0 – REFRESH[9:0]: SDRAM Refresh Period
This register sets the refresh period as a number of ClkPER2 cycles. If the EBI is busy with another external memory
access at time of refresh, up to 4 refresh will be remembered and given at the first available time.
24.9.4 INITDLY – SDRAM Initialization Delay register
Bit 15:14 – Reserved
These bits are unused and reserved for future use.
Bit 13:0 – INITDLY[13:0]: SDRAM Initialization Delay
This register is used to delay the initialisation sequence after the controller is enabled until all voltages are stabilized and
the SDRAM clock has been running long enough to take the SDRAM chip through its initialisation sequence. The
initialisation sequence includes pre-charge all banks to their idle state issuing an auto-refresh cycle and then loading the
mode register. The setting in this register is as a number of ClkPER2 cycles.
SDCOL[1:0]
Group configuration
Description
00
8BIT
8 column bits
01
9BIT
9 column bits
10
10BIT
10 column bits
11
11BIT
11 column bits
Bit
7
6543
210
+0x04
REFRESH[7:0]
Read/Write
R/W
Initial Value
0
0000
000
Bit
7
6543
210
+0x05
–
REFRESH[9:8]
Read/Write
RRRRR
R
R/W
Initial Value
0
0000
000
Bit
7
65
43
210
+0x06
INITDLY[7:0]
Read/Write
R/W
Initial Value
0
Bit
7
65
43
21
0
+0x07
–
INITDLY[13-8]
Read/Write
R
R/W
Initial Value
0
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