參數(shù)資料
型號： MF180C51T-25R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 83/170頁
文件大?。?/td> 4133K
代理商： MF180C51T-25R
2
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
1.
Pin Configurations
Figure 1-1.
Pinout of ATtiny4/5/9/10
1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB3..PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output
buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins
that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 36.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 16-4
on page 118. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1
2
3
6
5
4
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0
GND
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
PB3 (RESET/PCINT3/ADC3)
VCC
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
SOT-23
1
2
3
4
8
7
6
5
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
NC
GND
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
VCC
PB3 (RESET/PCINT3/ADC3)
PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)
UDFN
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