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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
9.8.1
Analog to digital converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
9.8.2
Analog comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is
automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will
figure the Analog Comparator.
9.8.3
Brown-out detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out
Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to
9.8.4
Internal voltage reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator
or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to
9.8.5
Watchdog timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
how to configure the Watchdog Timer.
9.8.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O) and the ADC clock
(clk
ADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section
“I/O-ports” on page 60 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or have an analog signal level close to V
CC/2, the input buffer
will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
9.8.7
On-chip debug system
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the main clock source is
enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the
total current consumption.