![](http://datasheet.mmic.net.cn/90000/MEGA32M1-15AZ_datasheet_3507761/MEGA32M1-15AZ_250.png)
250
7647F–AVR–04/09
ATmega16/32/64/M1/C1
18.9.6
Digital Input Disable Register 1– DIDR1
Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD,
AMP1ND, AMP2PD:
ADC10..8, ACMP0, ACMP1, ACMP3, AMP0P, AMP0N, AMP1P, AMP1N, AMP2P Digital
Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
18.10 Amplifier
The ATmega16/32/64/M1/C1 features three differential amplified channels with programmable
5, 10, 20, and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a synchro-
nization signal called in this document the amplifier synchronization clock. To ensure an
accurate result, the amplifier input needs to have a quite stable input value during at least 4
Amplifier synchronization clock periods. The amplifiers can run with a clock frequency of up to
250 kHz (typical value).
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the
sampling point during at least 4 amplifier synchronization clock periods.
ADC equal to eighth the ADC clock
frequency. In case the synchronization is done the ADC clock divided by 8, this synchronization
is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a
specific phase of CK
ADC2. A conversion initiated by the user (i.e., all single conversions, and the
first free running conversion) when CK
ADC2 is low will take the same amount of time as a single
ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initi-
ated by the user when CK
ADC2 is high will take 14 ADC clock cycles due to the synchronization
mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits
in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is done
on each synchronization event.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX
The ADC starting requirement is done by setting the ADSC bit of the ADCSRA Register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, two
Bit
76543210
-
AMP2PD
ACMP0D
AMP0PD
AMP0ND
ADC10D
ACMP1D
ADC9D
AMP1PD
ACMP3D
ADC8D
AMP1ND
DIDR1
Read/Write
-
R/W
Initial Value
00000000