118
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Table 15-2 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI
Data Register and the 4-bit counter.
Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the counter to increment by
one, provided that the software clock strobe option has been selected by writing USICS[1:0] bits to zero. The out-
put will change immediately when the clock strobe is executed, i.e., during the same instruction cycle. The value
shifted into the USI Data Register is sampled the previous instruction cycle.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a
Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-
The bit will be read as zero.
Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is inde-
pendent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the
corresponding DDR pin must be set as output (to one). This feature allows easy clock generation when implement-
ing master devices.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC
strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when oper-
ating as a master device.
The bit will read as zero.
Table 15-2.
Relationship between the USICS[1:0] and USICLK Setting
USICS1
USICS0
USICLK
Clock Source
4-bit Counter Clock Source
0
No Clock
0
1
Software clock strobe (USICLK)
0
1
X
Timer/Counter0 Compare Match
1
0
External, positive edge
External, both edges
1
0
External, negative edge
External, both edges
1
0
1
External, positive edge
Software clock strobe (USITC)
1
External, negative edge
Software clock strobe (USITC)