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參數(shù)資料
| 型號： | MD82C59A-5/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | 中斷控制器 |
| 英文描述： | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 436K |
| 代理商： | MD82C59A-5/B |
6
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
During the third INTA pulse, the higher address of the appro-
priate service routine, which was programmed as byte 2 of the
initialization sequence (A8 - A15), is enabled onto the bus.
D7
D6
D5
D4
D3
D2
D1
D0
Call Code
1100
1101
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR
I/OW
INT
INTA
CASCADE
LINES
CAS 0
CAS 1
CAS 2
SP/EN
CS
RD
WR
INTA
INT
D7 - D0
A0
SLAVE PROGRAM/
ENABLE BUFFER
INTERRUPT
REQUESTS
82C59A
IRQ
7
6
5
4
3
2
1
0
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR
INTERVAL = 4
D7
D6
D5
D4
D3
D2
D1
D0
7
A7
A6
A5
11100
6
A7
A6
A5
11000
5
A7
A6
A5
10100
4
A7
A6
A5
10000
3
A7
A6
A5
01100
2
A7
A6
A5
01000
1
A7
A6
A5
00100
0
A7
A6
A5
00000
IR
INTERVAL = 8
D7
D6
DS
D4
D3
D2
D1
D0
7
A7
A6
111000
6
A7
A6
110000
5
A7
A6
101000
4
A7
A6
100000
3
A7
A6
011000
2
A7
A6
010000
1
A7
A6
001000
0
A7
A6
000000
82C59A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR82C59A/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28 |
| MD82C59A-12/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28 |
| MD82C59A-5/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28 |
| MR82C59A-5/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28 |
| MR82C59A/B | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD82C59AB | 制造商:HARRIS 功能描述:* |
| MD82C82 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Bus Driver |
| MD82C82/B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Bus Driver |
| MD82C82B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Bus Driver |
| MD82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
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