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| 型號(hào)： | MD80C52TXXX-30:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 79/257頁(yè) |
| 文件大?。?/td> | 1840K |
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17
ATmega8515(L)
2512K–AVR–01/10
SRAM Data Memory
Figure 9 shows how the ATmega8515 SRAM Memory is organized.
The lower 608 Data Memory locations address the Register File, the I/O Memory, and
the internal data SRAM. The first 96 locations address the Register File and I/O Mem-
ory, and the next 512 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega8515. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. The Register File, I/O, Extended I/O
and Internal SRAM occupies the lowest 608 bytes in normal mode, so when using 64KB
(65536 bytes) of External Memory, 64928 Bytes of External Memory are available. See
“External Memory Interface” on page 25 for details on how to take advantage of the
external memory map.
When the addresses accessing the SRAM memory space exceeds the internal Data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal Data memory access. When the internal data memories are accessed,
the read and write strobe pins (PD7 and PD6) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
two-byte Program Counter is pushed and popped, and external memory access does
not take advantage of the internal pipe-line memory access. When external SRAM inter-
face is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruc-
tion set manual for one, two, and three wait-states.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of inter-
nal data SRAM in the ATmega8515 are all accessible through all these addressing
modes. The Register File is described in “General Purpose Register File” on page 11.
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