參數(shù)資料
型號(hào)： MD80C52TXXX-20P883D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 87/109頁(yè)
文件大小： 10824K
代理商： MD80C52TXXX-20P883D
64
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits are written. For non-PWM
modes, the action can be forced to have immediate effect by using the Force Output Compare bits. See “TCCR0B –
11.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM[2:0]) and Compare Output mode (COM0x[1:0]) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The
COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
For non-PWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or toggled at a Compare
11.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM0[2:0] = 0). In this mode the counting direction is always up
(incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value
(TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will
be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the
TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate
waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
11.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM0[2:0] = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 11-5 on page 64. The counter value (TCNT0) increases until a
Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
Figure 11-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a
TCNTn
OCnA
(Toggle)
OCnx Interrupt Flag Set
1
4
Period
2
3
(COMnA[1:0] = 1)
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