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參數(shù)資料
| 型號： | MD80C52TXXX-16SHXXX:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 64/125頁 |
| 文件大?。?/td> | 6456K |
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230
32117D–AVR-01/12
AT32UC3C
14.6.2
Event Shaper (EVS) Operation
PEVC contains Event Shapers (EVS) for certain types of generators:
Asynchronous generators and/or external input
General-purpose waveforms like timer outputs or Generic Clocks
Each Event Shaper is responsible of shaping one input, prior to going through a PEVC channel:
Synchronize asynchronous external inputs
Apply any additional glich-filtering
Detect rise, fall, or both edges of the incoming signal
14.6.2.1
Input Glitch Filter (IGF)
Input Glitch Filtering can be turned on or off by writing to the Input Glitch Filter (IGF) field of the
corresponding Event Shaper Register (EVS).
When IGF is on, the incoming event is sampled periodically. The sampling clock is divided from
CLK_RCSYS by the value of the Input Glitch Filter Divider Register (IGFDR). IGF will filter out
spikes and propagate only incoming events that respect one of the following two conditions :
rise event : 2 samples low, followed by 0+ changes, followed by 2 samples high
fall event : 2 samples high, followed by 0+ changes, followed by 2 samples low
Both CLK_RCSYS and CLK_PEVC must be enabled to use Input Glitch Filtering.
14.6.3
Event Propagation Latency
Once a channel is setup, incoming peripheral events are relayed by hardware. Event progation
latency is therefore cycle deterministic. However, its value depends on the exact settings that
apply to a given channel.
When the channel multiplexer CHMXn.EVMX selects a generator without Event Shaper, event
propagation latency is 0 cycle. Software event is a particular case of 0 cycle propagation.
When the channel multiplexer CHMXn.EVMX selects a generator with Event Shaper, event
propagation latency depends on Input Glitch Filter setting EVSm.IGF :
IGF off : event propagation latency is lesser or equal to 2 CLK_PEVC cycles
IGF on : event propagation latency is lesser or equal to 3 * 2IGFDR+1 * CLK_RCSYS cycles
Please refer to the Module Configuration section at the end of this chapter for the list of genera-
tors implementing Event Shapers.
Table 14-2.
Event Propagation Latency
Generator
CHMXn.EVMX
Input Glitch Filter
EVSm.IGF
Latency
Clock
Generator without Event Shaper
-
0
-
Software event
-
0
-
Generator with Event Shaper
Off
2
CLK_PEVC
Generator with Event Shaper
On
3 * 2IGFDR+1
CLK_RCSYS
相關PDF資料 |
PDF描述 |
|---|---|
| MR80C52CXXX-12SCR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52XXX-25 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-16SBD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MD80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C862 | 制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR |
| MD80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C86-2/883 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CPU 16BILT 5V CMOS 8MHZ 40CDIP - Bulk |
| MD80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube |
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