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參數(shù)資料
| 型號： | MD80C52EXXX-36/883:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 25028K |
106
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Table 15-7 on page 106 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set
to phase correct PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM mode” on
page 101 for more details.
Bits 3:2 – Reserved
These bits are reserved bits in the Atmel
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and will always read as zero.
Bits 1:0 – WGM01:0: Waveform Generation mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 15-8 on page 106. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode,
and two types of Pulse Width Modulation (PWM) modes (see ”Modes of Operation” on page
Notes:
1. MAX
= 0xFF
2. BOTTOM = 0x00
Table 15-7.
Compare Output mode, Phase Correct PWM mode (1).
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
01
Reserved
10
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
11
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 15-8.
Waveform Generation mode bit description.
Mode
WGM2
WGM1
WGM0
Timer/Counter
mode of
operation
TOP
Update of
OCRx at
TOV Flag
set on
0
Normal
0xFF
Immediate
MAX
10
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
Reserved
–
51
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
0
Reserved
–
7
1
Fast PWM
OCRA
BOTTOM
TOP
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