38
7530J–AVR–03/12
Atmel ATmega48/88/168 Automotive
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
7.4
Power-save Mode
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from
either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding
Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in
SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is
stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for Timer/Counter2.
7.5
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
Notes:
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
Table 7-2.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CPU
clk
FLASH
cl
k
IO
clk
ADC
clk
ASY
Ma
in
Cloc
k
Sour
ce
Enab
led
Timer
Oscillator
Enab
led
INT1,
I
N
T0
and
Pin
Ch
ange
TW
IAddress
Match
Timer2
SPM/EEPR
OM
Rea
d
y
ADC
WDT
Ot
herI
/O
Idle
XXX
X
X
XXX
X
ADC Noise
Reduction
XX
X
XXX
X
Power-down
XX
Power-save
X
XX
X
XX