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參數(shù)資料
| 型號： | MD80C32XXX-12/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 36/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MD80C32XXX-12/883 |
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280
7593L–AVR–09/12
AT90USB64/128
Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 23.15, page 271 for more details.
Shall be cleared by software. Setting by software has no effect.
5 - UNDERFI - Flow Error Interrupt flag
Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 23.15, page 271 for more details.
Shall be cleared by software. Setting by software has no effect.
4 - Reserved
The value read from these bits is always 0. Do not set these bits.
3-2 - DTSEQ1:0 - Data Toggle Sequencing flag
Set by hardware to indicate the PID data of the current bank:
00b
Data0
01b
Data1
1xb
Reserved
For OUT transfer, this value indicates the last data toggle received on the current bank.
For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not
relative to the current bank.
1-0 - NBUSYBK1:0 - Busy Bank flag
Set by hardware to indicate the number of busy bank.
For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.
For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the
host.
00b
All banks are free
01b
One busy bank
10b
Two busy banks
11b
Reserved
7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit
7
65
43
2
1
0
-
CTRLDIR
CURRBK1:0
UESTA1X
Read/write
RR
R
Initial value
0
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