
208
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
20.6.2
LINSIR – LIN Status and Interrupt Register
Bits 7:5 - LIDST[2:0]: Identifier Status
The LIN Identifier status is set according to
Table 20-8.
Bit 4 - LBUSY: Busy Signal
–0 = Not busy
– 1 = Busy (receiving or transmitting)
Bit 3 - LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR -
is set in LINENIR.
–0 = No error
– 1 = An error has occurred
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
Table 20-7.
LIN commands.
LCMD[2:0]
Mode
000
LIN Rx Header - LIN abort
001
LIN Tx Header
010
LIN Rx Response
011
LIN Tx Response
100
UART Rx & Tx Byte disable
11x
UART Rx Byte enable
1x1
UART Tx Byte enable
Bit
76543210
LIDST2
LIDST1
LIDST0
LBUSY
LERR
LIDOK
LTXOK
LRXOK
LINSIR
Read/write
RRRR
R/W
one
R/W
one
R/W
one
R/W
one
Initial value
00000000
Table 20-8.
LIN identifier status
LIDST[2:0]
Status
0xx
No specific identifier
100
Identifier 60 (0x3C)
101
Identifier 61 (0x3D)
110
Identifier 62 (0x3E)
111
Identifier 63 (0x3F)