143
8019K–AVR–11/10
ATmega165P
16.11 Register Description
16.11.1
TCCR2A – Timer/Counter Control Register A
Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A[1:0] bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A[1:0] bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
Bit 6, 3 – WGM2[1:0]: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
Note:
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM2[1:0] definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
Bit 5:4 – COM2A[1:0]: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0]
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the
WGM2[1:0] bit setting.
Bit
7
6
5
4
3
210
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
TCCR2A
Read/Write
W
R/W
Initial Value
0
Table 16-2.
Waveform Generation Mode Bit Description
Mode
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode of
Operation
TOP
Update of
OCR2A at
TOV2 Flag
Set on
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
1
0
CTC
OCR2A
Immediate
MAX
3
1
Fast PWM
0xFF
BOTTOM
MAX