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參數(shù)資料
| 型號(hào)： | MD80C32-30 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 15/210頁(yè) |
| 文件大小： | 5175K |
| 代理商： | MD80C32-30 |
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111
8048C–AVR–02/12
ATtiny43U
Table 14-2 shows the relationship between the USICS[1:0] and USICLK setting and clock
source used for the USI Data Register and the 4-bit counter.
Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the counter
to increment by one, provided that the software clock strobe option has been selected by writing
USICS[1:0] bits to zero. The output will change immediately when the clock strobe is executed,
i.e., during the same instruction cycle. The value shifted into the USI Data Register is sampled
the previous instruction cycle.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see Table 14-2).
The bit will be read as zero.
Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the corresponding DDR pin must be set as output (to one). This feature
allows easy clock generation when implementing master devices.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
The bit will read as zero.
14.5.2
USISR – USI Status Register
The Status Register contains interrupt flags, line status flags and the counter value.
Bit 7 – USISIF: Start Condition Interrupt Flag
When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has
been detected. When three-wire mode or output disable mode has been selected any edge on
the SCK pin will set the flag.
Table 14-2.
Relationship between the USICS[1:0] and USICLK Setting
USICS1
USICS0
USICLK
Clock Source
4-bit Counter Clock Source
0
No Clock
0
1
Software clock strobe (USICLK)
0
1
X
Timer/Counter0 Compare Match
1
0
External, positive edge
External, both edges
1
0
External, negative edge
External, both edges
1
0
1
External, positive edge
Software clock strobe (USITC)
1
External, negative edge
Software clock strobe (USITC)
Bit
7
6
5
4
3
2
1
0
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
USISR
Read/Write
R/W
R
R/W
Initial Value
0
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