
260
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Note:
1. The differential input channels are not tested for devices in PDIP Package. This feature is only
guaranteed to work for devices in TQFP and VQFN/QFN/MLF Packages.
Table 23-4.
Input channel and gain selections.
MUX4..0
Single ended
input
Positive differential input
Negative differential input
Gain
00000
ADC0
00001
ADC1
00010
ADC2
00011
ADC3
N/A
00100
ADC4
00101
ADC5
00110
ADC6
00111
ADC7
01000
ADC0
10×
01001
ADC1
ADC0
10×
ADC0
200×
ADC1
ADC0
200×
01100
ADC2
10×
01101
ADC3
ADC2
10×
ADC2
200×
ADC3
ADC2
200×
10000
ADC0
ADC1
1×
10001
ADC1
1×
10010
N/A
ADC2
ADC1
1×
10011
ADC3
ADC1
1×
10100
ADC4
ADC1
1×
10101
ADC5
ADC1
1×
10110
ADC6
ADC1
1×
10111
ADC7
ADC1
1×
11000
ADC0
ADC2
1×
11001
ADC1
ADC2
1×
11010
ADC2
1×
11011
ADC3
ADC2
1×
11100
ADC4
ADC2
1×
11101
ADC5
ADC2
1×
11110
1.1V (VBG)
N/A
11111
0 V (GND)