參數(shù)資料
型號: MCZ33970EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Dual Gauge Driver Integrated Circuit with Improved Damping Algorithms
中文描述: 雙計驅(qū)動集成電路與改進(jìn)的阻尼算法
文件頁數(shù): 16/36頁
文件大小: 430K
代理商: MCZ33970EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
33970
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The bits in
Table 9
are
write-only
.
P0 12 (D12) — This bit must be transmitted as logic [0] for
valid commands.
P0 11:P0 0 (D11:D0) — Desired pointer position of
Gauge 0. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25
°.
.
Table 10. Gauge 1 Position Register (POS1R)
The bits in
Table 10
are
write-only
.
P1 12 (D12) — This bit must be transmitted as logic [0] for
valid commands.
P1 11:P1 0 (D11:D0) — Desired pointer position of
Gauge 1. Pointer positions can range from 0
(000000000000) to position 4095 (111111111111). For a
step motor requiring 12 microsteps per degree of pointer
movement, the maximum pointer sweep is 341.25
°
(4095
÷
12).
Address 100 — Gauge Return to Zero Register (RTZR)
Gauge Return to Zero Register (RTZR) (refer to
Table 11
)
is written to return the gauge pointers to the zero position.
During an RTZ event, the pointer is returned to zero using full
steps, where only one coil is driven at any point in time. The
back electromotive force (EMF) signal present on the non-
driven coil is integrated and its results are stored in an
accumulator.
A logic [1] written to bit RZ1 enables a Return to Zero for
Gauge 0 if RZ0 is logic [0], and Gauge 1 if RZ0 is logic [1],
respectively. Similarly, a logic [0] written to bit RZ1 disables a
Return to Zero for Gauge 0 when RZ0 is logic [0], and
Gauge 1 when RZ0 is logic [1], respectively.
Bits D12:D5 and D3:D2 must be at logic [0] for valid RTZR
commands.
Bit RZ4 is used to enable an unconditional RTZ event. A
logic [0] results in a typical RTZ event, automatically
providing a Stop when a stall condition is detected. A logic [1]
will result in RTZ movement, causing a Stop if a logic [0] is
written to bit RZ0. This feature is useful during development
and characterization of RTZ requirements.
The register bits in
Table 11
are
write-only
.
RZ12:RZ5 (D12:D5) — These bits must be transmitted as
logic [0] for valid commands.
RZ4 (D4) — This bit is used to enable an unconditional
RTZ event.
0 = Automatic Return to Zero
1 = Unconditional Return to Zero
RZ3 (D3) — This bit must be transmitted as logic [0] for
valid commands.
RZ2 (D2) — Return to Zero Direction bit. This bit is used to
properly sequence the integrator, depending upon the
desired zeroing direction.
0 = Return to Zero will occur in the CCW direction
(PE7 = 0)
1 = Return to Zero will occur in the CW direction
(PE7 = 1)
Table 9. Gauge 0 Position Register (POS0R)
Address 010
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
Write
0
P0 11
P0 10
P0 9
P0 8
P0 7
P0 6
P0 5
P0 4
P0 3
P02
P01
P0 0
Address 011
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
Write
0
P1 11
P1 10
P1 9
P1 8
P1 7
P1 6
P1 5
P1 4
P1 3
P1 2
P1 1
P1 0
Table 11. Return to Zero Register (RTZR)
Address 100
Bits
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read
Write
0
0
0
0
0
0
0
0
RZ4
0
RZ2
RZ1
RZ0
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