DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號: MCZ33905S5EK
廠商: Freescale Semiconductor
文件頁數(shù): 84/106頁
文件大?。?/td> 0K
描述: IC SYSTEM BASIS CHIP GEN2 32SOIC
標準包裝: 42
應用: 系統(tǒng)基礎芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 27 V
封裝/外殼: 32-BSOP(0.295",7.50mm 寬)裸露焊盤
供應商設備封裝: 32-SOICW 裸露焊盤
包裝: 管件
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
79
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 34. CAN Register(42)
MOSI First byte [15-8]
[b_15 b_14] 10_000 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 000P
CAN mod[1]
CAN mod[0]
Slew[1]
Slew[0]
Wake-up 1/3
-
CAN int
Default state
1
0
-
0
Condition for default
note
POR
Bits
Description
b7 b6
CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable
00
CAN interface in Sleep mode, CAN Wake-up disable.
01
CAN interface in receive only mode, CAN driver disable.
10
CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode,
CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT.
11
CAN interface in transmit and receive mode.
b5 b4
Slew[1] Slew[0] - CAN driver slew rate selection
00/11
FAST
01
MEDIUM
10
SLOW
b3
Wake-up 1/3 - Selection of CAN Wake-up mechanism
0
3 dominant pulses Wake-up mechanism
1
Single dominant pulse Wake-up mechanism
b0
CAN INT - Select the CAN failure detection reporting
0
Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN)
1
Select INT generation as soon as a bus failure is detected, event if not fully identified
Notes
42.
The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is
set in Normal mode, the CAN state is controlled by bits 7 and 6.
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