CYCLIC SENSE OPERATION DURING LP MODES " />
參數(shù)資料
型號(hào)： MCZ33904A5EKR2
廠商： Freescale Semiconductor
文件頁數(shù)： 49/106頁
文件大?。?/td> 0K
描述： IC SYSTEM BASIS CHIP 32-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 27 V
封裝/外殼： 32-BSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
33903/4/5
FUNCTIONAL DEVICE OPERATION
CYCLIC SENSE OPERATION DURING LP MODES
CYCLIC SENSE OPERATION DURING LP MODES
This function can be used in both LP modes: VDD OFF and
VDD ON.
Cyclic sense is the periodic activation of I/O-0 to allow
biasing of external contact switches. The contact switch state
can be detected via I/O-1, -2, and -3, and the device can
Wake-up from either LP mode.
Cyclic sense is optimized and designed primarily for
closed contact switch in order to minimize consumption via
the contact pull-up resistor.
Principle
A dedicated timer provides an opportunity to select a cyclic
sense period from 3.0 to 512 ms (selection in timer B).
At the end of the period, the I/O-0 will be activated for a
duration of T_CSON (SPI selectable in INIT register, to 200 s,
400
s, 800 s, or 1.6 ms). The I/O-0 HS transistor or LS
transistor can be activated. The selection is done by the state
of I/O-0 prior to entering in LP mode.
During the T-CSON duration, the I/O-x’s are monitored. If
one of them is high, the device will detect a Wake-up.
Cyclic sense period is selected by the SPI configuration
prior to entering LP mode. Upon entering LP mode, the I/O-0
should be activated.
The level of I/O-1 is sense during the I/O-0 active time, and
is deglitched for a duration of typically 30
s. This means that
I/O-1 should be in the expected state for a duration longer
than the deglitch time.
The diagram below (Figure 26) illustrates the cyclic sense
operation, with I/O-0 HS active and I/O-1 Wake-up at high
level.
Figure 26. Cyclic Sense Operation - Switch to GND, Wake-up by Open Switch
I/O-0
I/O-1
NORMAL MODE
LP MODE
I/O-0 HS active in Normal mode
I/O-0 HS active during cyclic sense active time
Cyclic sense period
Cyclic sense active time
RESET or NORMAL REQUEST MODE
Wake-up detected.
state of I/O-1 low => no Wake-up
Cyclic sense active
I/O-1 deglitcher time
I/O-1 high => Wake-up
I/O-0
I/O-1
Zoom
time (ex 200 us)
Wake-up event detected
I/O-0
I/O-1
S1 closed
S1 open
S1
(typically 30 us)
S1
R
I/O-2
R
S2
R
S3
I/O-3
I/O-0
I/O-1
S1
R
I/O-2
R
S2
R
S3
I/O-3
Upon entering in LP mode, all 3
contact switches are closed.
In LP mode, 1 contact switch is open.
High level is detected on I/O-x, and device wakes up.
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MCZ33904A5EK IC SYSTEM BASIS CHIP 32-SOIC
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參數(shù)描述
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MCZ33904B5EK 功能描述:CAN 接口集成電路 5V SBC HI SPEED CAN RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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