DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號(hào)： MCZ33904A5EK
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 76/106頁(yè)
文件大小： 0K
描述： IC SYSTEM BASIS CHIP 32-SOIC
標(biāo)準(zhǔn)包裝： 42
應(yīng)用： 系統(tǒng)基礎(chǔ)芯片
接口： CAN，LIN
電源電壓： 5.5 V ~ 27 V
封裝/外殼： 32-BSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
71
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
b0
Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND
0
VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset mode
1
VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1)
Table 19. Initialization LIN and I/O Registers, INIT LIN I/O (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0111 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 00 _ 111 P
I/O-1 ovoff
LIN_T2[1]
LIN_T2[0]
LIN_T/1[1]
LIN_T/1[0]
I/O-1 out-en
I/O-0 out-en
Cyc_Inv
Default state
0
Condition for default
POR
Bit
Description
b7
I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX overvoltage condition is detected
0
Disable I/O-1 turn off.
1
Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected.
b6, b5
LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O
00
pin is OFF
01
pin operation as LIN Master pin switch
10
pin operation as I/O: HS switch and Wake-up input
11
N/A
b4, b3
LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O
00
pin is OFF
01
pin operation as LIN Master pin switch
10
pin operation as I/O: HS switch and Wake-up input
11
N/A
b2
I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS)
0
Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input.
1
Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver.
b1
I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS)
0
Disable HS and LS drivers of I/O-0 can only be used as input.
1
Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers.
b0
Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected
0
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0 is disable (HS and
LS drivers OFF).
1
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the opposite driver of I/
O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration of the active time, for the duration of
the cyclic sense period.
Bit
Description
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