DETAIL OF CONTROL BITS AND REGISTER MAPPING" />
參數(shù)資料
型號: MCZ33903B3EKR2
廠商: Freescale Semiconductor
文件頁數(shù): 87/106頁
文件大?。?/td> 0K
描述: IC SBC CAN HS 3.3V 32SOIC
標準包裝: 1,000
應(yīng)用: 系統(tǒng)基礎(chǔ)芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 28 V
封裝/外殼: 32-BSOP(0.295",7.50mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 32-SOICW 裸露焊盤
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
81
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 36. INT Register
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 10_ 010P
CAN failure
MCU req
LIN2 fail
LIN1fail
I/O
SAFE
-
Vmon
Default state
0
Condition for default
POR
Bits
Description
b7
CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN overcurrent, Driver Overtemp, TXD-PD,
RXD-PR, RX2HIGH, and CANBUS Dominate clamp)
0
INT disable
1
INT enable.
b6
MCU req - Control bit to request an INT. INT will occur once when the bit is enable
0
INT disable
1
INT enable.
b5
LIN2 fail - Control bit to enable INT when of failure on LIN2 interface
0
INT disable
1
INT enable.
b4
LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface
0
INT disable
1
INT enable.
b3
I/O - Bit to control I/O interruption: I/O failure
0
INT disable
1
INT enable.
b2
SAFE - Bit to enable INT when of: Vaux overvoltage, VDD overvoltage, VDD Temp pre-warning, VDD undervoltage(43), SAFE
resistor mismatch, RST terminal short to VDD, MCU request INT.(44)
0
INT disable
1
INT enable.
b0
VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Overcurrent, VSUV,
VSOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX overcurrent
0
INT disable
1
INT enable.
Notes
43.
If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69.
44.
Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.
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