OPERATIONAL MODES Figure 6. DBUS Slave Logic" />
參數(shù)資料
型號: MCZ33784EF
廠商: Freescale Semiconductor
文件頁數(shù): 7/30頁
文件大小: 0K
描述: IC SENSOR DBUS DSI 2.02 16-SOIC
標準包裝: 48
類型: 傳感器接口
輸入類型: 模擬
輸出類型: 數(shù)字
接口: 總線
電流 - 電源: 4mA
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 管件
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
33784
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 6. DBUS Slave Logic Block Diagram
COMMUNICATION FORMAT
DBUS messages are composed of individual words
separated by a frame delay. Transfers are full duplex.
Command messages from the master occur at the same time
as responses from the slaves. Slave responses to commands
occur during the next command message. This allows slaves
time to decode the command, retrieve the information, and
prepare to send it to the master. A bus traffic example is
shown in Figure 7.
The example shows three commands separated by the
minimum frame delay followed by a command after a longer
delay.
Figure 7. Bus Traffic Example
Bus Controller
10MHz Clock
Command Buffer
CRC
Check
Latch
Data
Data Clock
Load Enable
Response Shifter
CRC Generator
Data Clock
SEL
IResponse ON
10MHz Clock
Received Message
From MASTER
DBUS Registers
INIT
REQ STATUS
REQ AN0
I/O CONTROL
REQ ID
REQ AN1
CLEAR
FORMAT CONTROL
TEST
DATA OUT [2:0]
I/O [2:0]
AD_SEL
AD_DATA [9:0]
F
ra
m
e_OK
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