參數(shù)資料
型號: MCZ33291LEG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Eight-Output Switch with Serial Peripheral Interface I/O
中文描述: 8輸出開關(guān)串行外設(shè)接口的I / O
文件頁數(shù): 7/25頁
文件大小: 389K
代理商: MCZ33291LEG
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33291L
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Notes
14.
SPI inputs and outputs operational. Fault status reporting may not be fully operational within this voltage range. Outputs remain
operational somewhat below this V
PWR
range, but R
DS(ON)
will increase, causing power dissipation to increase. Outputs will re-
establish their instructed state following a V
PWR
interruption as long as V
DD
remains non-interrupted.
This parameter is guaranteed by design, but it is not production tested.
Measured with the
RST
pin held at a logic high state. Outputs can be OFF or ON or in any combination thereof.
Device incorporates a power-ON reset function. For V
DD
less than the Undervoltage Lockout Threshold voltage, all data registers are
reset and all outputs are disabled.
Output Fault Detect Threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts.
Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded to be OFF.
15.
16.
17.
18.
19.
Output Clamp Voltage
2.0 mA < I
OUT
< 200 mA
V
OK
45
53
65
V
Output Leakage Current (V
DD
< 2.0 V)
(20)
Overtemperature Shutdown (Outputs OFF)
(21)
I
OUT(LKG)
-25
0
25
μ
A
T
LIM
155
180
°
C
Overtemperature Shutdown Hysteresis
(21)
T
LIM(HYS)
10
20
°
C
DIGITAL INTERFACE
Input Logic High Voltage
(22)
V
IH
0.7
1.0
V
DD
Input Logic Low Voltage
(22)
V
L
0
0.2
V
DD
Input Logic Threshold Hysteresis (SCLK,
RST
, and SFPD)
(23)
V
I (HYS)
50
100
500
mV
SI Pull-Up Current (SI = 0 V)
I
SI
0
10
20
μ
A
CS
Pull-Up Current (
CS
= 0 V)
I
CS
0
10
20
μ
A
SCLK Pull-Down Current (SCLK = 5.0 V)
I
SCLK
0
10
20
μ
A
RST
Pull-Down Current (
RST
= 5.0 V)
I
RST
5.0
25
50
μ
A
SFPD Pull-Down Current (SFPD = 5.0 V)
I
SFPD
5.0
10
25
μ
A
SO High-State Output Voltage (I
OH
= 1.0 mA)
V
SOH
V
DD
- 0.4 V V
DD
- 0.2 V
V
SO Low-State Output Voltage (I
OL
= -1.6 mA)
V
SOL
0.2
0.4
V
SO Tri-State Leakage Current (
CS
= 0.7 VDD, 0 V < V
SO
< V
DD
)
Input Capacitance (0 V < V
DD
< 5.5 V)
(24)
SO Tn-State Capacitance (0 V < V
DD
< 5.5 V)
(25)
I
SOT
-10
0
10
μ
A
C
IN
12
pF
C
SOT
20
pF
Notes
20.
21.
22.
23.
24.
Output leakage current measured with the output OFF and at 16 V.
This parameter is guaranteed by design, but it is not production tested.
Upper and lower logic threshold voltage levels apply to SI,
CS
, SCLK,
RST
, and SFPD inputs.
Hysteresis is characterized, but it is not production tested.
Input capacitance of SI
CS
, SCLK,
RST
, and SFPD for 0 V < V
DD
< 5.5 V. This parameter is guaranteed by design, but it is not production
tested.
Tri-state capacitance of SO for 0 V < V
DD
< 5.5 V. This parameter is guaranteed by design, but it is not production tested.
25.
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V
V
DD
5.5 V, 9.0 V
V
PWR
16 V, -40
°
C
T
A
125
°
C, unless otherwise noted.
Typical values noted reflect the approximate value with V
BAT
= 13 V, T
A
= 25
°
C.
Characteristic
Symbol
Min
Typ
Max
Unit
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