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參數(shù)資料
| 型號： | MCZ33094EGR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC IGNITION CONTROL 12V 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 自動 |
| 電源電壓： | 6 V ~ 16 V |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
33094
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
IGNITION CIRCUIT OPERATION DESCRIPTION
When initially powered up, all module capacitors start
discharged (0V). The VCC capacitor will power up first, and
the IC’s internal logic latches are indeterminate. The following
conditions will hold: STALL = 1, because the stall capacitor
voltage is less than 2.0 V; 25% = 0, because the ramp
capacitor is less than the Band Gap Reference voltage (VBG);
and ICOIL = 0 amps, because the stall capacitor is at 0V.
Because 25% = 0, the ramp capacitor charges towards Vr.
At cranking frequencies, the ramp capacitor always exceeds
the start mode threshold at the input (ZC or VIN-1), and
therefore the stall signal resets the start mode latch upon the
first ac signal (this causes the adaptive capacitor to be
discharged). With the adaptive capacitor held low, very high
rates of acceleration are possible. If the adaptive capacitor
were allowed to adapt the dwell at low frequencies, severe
limitations to engine acceleration would occur.
See Figure 15. At point A, a spark from the previous cycle
occurs as the field around the coil collapses rapidly. At the
same time ZC (VIN- > 10V) will set the 25% clock signal which
commands the adaptive and ramp capacitors to discharge
and the stall capacitor to charge. At point B, as the ramp
capacitor voltage crosses the 1.2V (VBG) level, the 25% clock
is cleared and the polarities and amplitude of the ramp and
stall capacitor currents change to their appropriate levels. At
this point the adaptive capacitor is discharged and begins to
float. At point C, the coil turns on and ramps until the coil
current is limited to 6.5 amps. The adaptive capacitor, at point
D, remains discharged and the dwell is maximized to 6.5
amps because the start/run latch has yet to be set. At point
E, ZC (VIN- > 10V, ZC = high) turns the coil off causing a
spark to occur and at which point a new cycle begins. As the
engine frequency increases, the peak voltage on the ramp
capacitor at the ac signal will fall below the start mode enable
threshold level. The start mode enable detector then sets the
start/run latch to the run mode (CADUMP = 0) by clocking a
zero into the start/run latch at the zero cross. At this time the
adaptive algorithm is evoked and the adaptive capacitor is
allowed to charge and discharge according to it’s other logical
inputs. After normal run mode operation is entered, the start
mode may not be reentered even though the ramp capacitor
voltage again exceeds the start mode enable threshold. A
start mode may only be evoked by a STALL signal transition
from logic 1 to 0. The STALL signal transition occurs at a VIN-
frequency of approximately 2.0 Hz.
The IC and circuit provides for other than normal starting
procedures such as push starting the engine. Since the stall
capacitor will be discharged in this low frequency mode, the
IC will provide a spark timing with a maximum retardation of
about 6.5ms.
After the start mode operation is exited, the normal
operation algorithm is entered and a different sequence of
events dominate the IC’s performance. See Figures 16, 17,
and 18. At point A, the spark from the previous cycle occurs
and the 25% part of the cycle begins. During this part of the
cycle, the stall capacitor will charge and the ramp and
adaptive capacitors will discharge. At point B, the “not 25%”
part of the cycle, also called the 75% part of the cycle, begins.
The stall capacitor discharges, while the ramp capacitor
charges. During this part of the cycle the adaptive capacitor
floats. At point C, the ramp capacitor voltage equals the
voltage on the adaptive capacitor. At this time, the coil turns
on and the coil current ramps to the point where it is limited.
When the coil current reaches the limit, point D, the adaptive
capacitor begins to charge, until zero cross
(ZC = 1logic(high)), point E. This turns the coil off and
induces a spark. The 75% part of the cycle lasts until point E,
at which time the cycle begins again.
The adaptive dwell algorithm causes the engine to
maintain a fixed percent of excess dwell time (if possible).
The mechanism that permits this involves the floating nature
of the adaptive capacitor. During engine deceleration, the
initial coil turn–on might occur early, but the next coil turn–on
will be retarded to it’s correct location due to the % adjusted
adaptive capacitor charge time. During acceleration, the coil
may not charge up as early as desired the first time, however,
the spark will still be correctly slaved to the distributor. The
side effect of this is that the adaptive capacitor will not receive
as much charge time for that cycle and will have a lower
average value the next cycle, thus starting the coil charging
sooner, as can be seen in Figure 17. In this figure, the output
voltage rises before the adaptive capacitor charge signal
occurs.
See Figure 13. In the Stall mode the output is slaved by the
stall capacitor. The stall capacitor can discharge completely,
but starting at point X it charges during the 25% of the engine
cycle (duration of when ZC is logic high = 1). At the same time
a spark from the previous cycle occurs. The DWELL signal
will be high as long as the engine is in stall, but falls gradually
preventing a spark at point Y when the STALL goes low
starting at 2.4V. The coil will be slaved to the stall capacitor,
and at point Z the coil will charge to 6.5 amps as the stall
capacitor charges to 2.0V. At that time the STALL comparator
will trip (STALL = 0) and the DWELL signal will fall, triggering
a reduced spark with some retardation (6.5ms). At this point
a new cycle begins.
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