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參數(shù)資料
| 型號(hào)： | MCV14ATI/SL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOIC-4 |
| 文件頁數(shù)： | 37/84頁 |
| 文件大小： | 1007K |
| 代理商： | MCV14ATI/SL |
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MCV14A
DS41338B-page 40
Preliminary
2009 Microchip Technology Inc.
7.3
Reset
The device differentiates between various kinds of
Reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Time-out Reset during normal operation
WDT Time-out Reset during Sleep
Wake-up from Sleep on pin change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF bits. They are set or cleared
differently in different Reset situations. These bits are
used in software to determine the nature of Reset. See
Table 7-3 for a full description of Reset states of all
registers.
TABLE 7-3:
RESET CONDITIONS FOR REGISTERS
Register
Address
Power-on Reset
MCLR Reset, WDT Time-out,
Wake-up On Pin Change
W
—
qqqq qqq
0
(1)
qqqq qqq0
(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
STATUS
03h
0001 1xxx
qq0q quuu
(2)
FSR
04h
100x xxxx
1uuu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
PORTB
06h
--xx xxxx
--uu uuuu
PORTC
07h
--xx xxxx
--uu uuuu
CMICON0
08h
q111 1111
quuu uuuu
ADCON0
09h
1111 1100
ADRES
0Ah
xxxx xxxx
uuuu uuuu
CM2CON0
0Bh
q111 1111
quuu uuuu
VRCON
0Ch
001-1111
uuu-uuuu
OPTION
—
1111 1111
TRISB
—
--11 1111
TRISC
—
--11 1111
EECON
21h/61h
---0 x000
---0 q000
EEDATA
25h/65h
xxxx xxxx
uuuu uuuu
EEADR
26h/66h
--xx xxxx
--uu uuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1:
Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2:
See Table 7-4 for Reset value for specific conditions.
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