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參數(shù)資料
| 型號： | MCP73832-4ADI/OT |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | PLASTIC, SC-74A, SOT-23, 5 PIN |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 786K |
| 代理商： | MCP73832-4ADI/OT |
2007 Microchip Technology Inc.
DS21984C-page 3
MCP73831/2
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
VDD...................................................................................7.0V
All Inputs and Outputs w.r.t. VSS ............... -0.3 to (VDD+0.3)V
Maximum Junction Temperature, TJ ............Internally Limited
Storage temperature .....................................-65°C to +150°C
ESD protection on all pins:
Human Body Model (1.5 k
Ω in Series with 100 pF).......≥ 4kV
Machine Model (200 pF, No Series Resistance) .............400V
Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all limits apply for VDD= [VREG(typical) + 0.3V] to 6V, TA = -40°C to +85°C.
Typical values are at +25°C, VDD = [VREG (typical) + 1.0V]
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Input
Supply Voltage
VDD
3.75
—
6
V
Supply Current
ISS
—
510
1500
A
Charging
—
53
200
A
Charge Complete,
No Battery
—
25
50
A
PROG Floating
—1
5
A
VDD < (VBAT - 50 mV)
—0.1
2
A
VDD < VSTOP
UVLO Start Threshold
VSTART
3.3
3.45
3.6
V
VDD Low-to-High
UVLO Stop Threshold
VSTOP
3.2
3.38
3.5
V
VDD High-to-Low
UVLO Hysteresis
VHYS
—70
—
mV
Voltage Regulation (Constant-Voltage Mode)
Regulated Output Voltage
VREG
4.168
4.20
4.232
V
MCP7383X-2
4.317
4.35
4.383
V
MCP7383X-3
4.367
4.433
V
MCP7383X-4
4.466
4.50
4.534
V
MCP7383X-5
VDD = [VREG(typical)+1V]
IOUT = 10 mA
TA = -5°C to +55°C
Line Regulation
|(ΔVBAT/
VBAT)/ΔVDD|
—
0.09
0.30
%/V
VDD = [VREG(typical)+1V] to
6V, IOUT = 10 mA
Load Regulation
|ΔVBAT/VBAT|
—
0.05
0.30
%
IOUT = 10 mA to 50 mA
VDD = [VREG(typical)+1V]
Supply Ripple Attenuation
PSRR
—
52
—-
dB
IOUT=10 mA, 10Hz to 1 kHz
—47
—
dB
IOUT=10 mA, 10Hz to 10 kHz
—22
—
dB
IOUT=10 mA, 10Hz to 1 MHz
Current Regulation (Fast Charge Constant-Current Mode)
Fast Charge Current
Regulation
IREG
90
100
110
mA
PROG = 10 k
Ω
450
505
550
mA
PROG = 2.0 k
Ω, Note 1
TA = -5°C to +55°C
Note 1:
Not production tested. Ensured by design.
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