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| 型號： | MCP6V31UT-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 16/40頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP SGL ZERO DRIFT SOT23-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 零漂移 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.13 V/µs |
| 增益帶寬積： | 300kHz |
| 電流 - 輸入偏壓： | 5pA |
| 電壓 - 輸入偏移： | 8µV |
| 電流 - 電源： | 23µA |
| 電流 - 輸出 / 通道： | 21mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MCP6V31UT-E/OTDKR |
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2012 Microchip Technology Inc.
DS25127A-page 23
MCP6V31/1U
4.3.8
GAIN PEAKING
Figure 4-10 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG rep-
resent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and non-
inverting input pins.
FIGURE 4-10:
Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
approximate limit for RF is:
EQUATION 4-2:
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small, in order to prevent
positive feedback and oscillations. Large CN values
can also help.
4.3.9
REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges
Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.10
SUPPLY BYPASSING AND
FILTERING
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm
of the pin for good high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 F or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
4.3.11
PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 V,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V31/1U op
amps’ minimum and maximum specifications.
4.3.11.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature.
The
following
are
examples
of
thermojunctions on a PCB:
Components (resistors, op amps, …) soldered to
a copper pad
Wires mechanically attached to the PCB
Jumpers
Solder joints
PCB vias
RG
RF
VOUT
U1
MCP6V3X
CG
RN
CN
VM
VP
CFP
R
F
10 k
Ω
() 12 pF
C
G
--------------
×
G
N
2
×
≤
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