V
參數(shù)資料
型號: MCP6N11T-100E/MNY
廠商: Microchip Technology
文件頁數(shù): 23/50頁
文件大?。?/td> 0K
描述: IC AMP INSTR RRIO 35MHZ 8TDFN
標準包裝: 1
放大器類型: 儀表
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 6 V/µs
增益帶寬積: 35MHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 350µV
電流 - 電源: 800µA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN(2x3)
包裝: 標準包裝
其它名稱: MCP6N11T-100E/MNYDKR
2011 Microchip Technology Inc.
DS25073A-page 3
MCP6N11
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings
VDD –VSS .......................................................................6.5V
Current at Input Pins ...............................................±2 mA
Analog Inputs (VIP and VIM) ..... VSS – 1.0V to VDD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage....................................... |VDD –VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, CDM, MM)
.≥ 2 kV, 1.5 kV, 300V
Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA =+25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL =VDD,
VCM =VDD/2, VDM =0V, VREF =VDD/2, VL =VDD/2, RL =10 kΩ to VL and GDM =GMIN; see Figure 1-6 and Figure 1-7.
Parameters
Sym
Min
Typ
Max
Units
GMIN
Conditions
Input Offset
Input Offset Voltage,
Calibrated
VOS
-3.0
+3.0
mV
1
-2.0
+2.0
mV
2
-0.85
+0.85
mV
5
-0.50
+0.50
mV
10
-0.35
+0.35
mV
100
Input Offset Voltage
Trim Step
VOSTRM
—0.36
mV
1
—0.21
mV
2
—0.077
mV
5
—0.045
mV
10
—0.014
mV
100
Input Offset Voltage
Drift
ΔVOS/ΔTA
—±90/GMIN
V/°C 1 to 10 TA= -40°C to +125°C
±2.7
V/°C
100
Power Supply
Rejection Ratio
PSRR
62
82
dB
1
68
88
dB
2
75
96
dB
5
81
102
dB
10
86
112
dB
100
Note 1:
VCM = (VIP + VIM) / 2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
2:
The VOS spec limits include 1/f noise effects.
3:
This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect.
4:
These specs apply to both the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (VREF takes VCM’s place).
5:
This spec applies to the VIP, VIM, VREF and VFG pins individually.
6:
Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature.
7:
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