參數(shù)資料
型號(hào)： MCP6566UT-E/OT
廠商： Microchip Technology
文件頁(yè)數(shù)： 6/30頁(yè)
文件大小： 0K
描述： IC COMPARATOR O-D 1.8V SOT23-5
產(chǎn)品培訓(xùn)模塊： MCP656x
標(biāo)準(zhǔn)包裝： 1
類型： 通用
元件數(shù)： 1
輸出類型： CMOS，開(kāi)路漏極
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
電壓 - 輸入偏移（最小值）： 10mV @ 5.5V
電流 - 輸入偏壓（最小值）： 1pA @ 5.5V
電流 - 輸出（標(biāo)準(zhǔn)）： 50mA
電流 - 靜態(tài)（最大值）： 130µA
CMRR, PSRR（標(biāo)準(zhǔn)）： 66dB CMRR，70dB PSRR
傳輸延遲（最大）： 80ns
磁滯： 5mV
工作溫度： -40°C ~ 125°C
封裝/外殼： SC-74A，SOT-753
安裝類型： 表面貼裝
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 681 (CN2011-ZH PDF)
其它名稱： MCP6566UT-E/OTDKR
22
DS580F6
CS8406
8.7
Interrupt 1 Status (07h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
TSLIP - AES3 transmitter source data slip interrupt
In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit
will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high
on receipt of a new TCBL signal.
EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in
the C bit buffer management process.
8.8
Interrupt 2 Status (08h) (Read Only)
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ me ans the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be ‘0’ in this register. This register defaults to 00h.
EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F
buffer transfer in the U bit buffer management process.
8.9
Interrupt 1 Mask (09h)
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is mas ked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h.
7
6
5
432
1
0
TSLIP
0
EFTC
0
7
6
5
432
1
0
00
0
EFTU
0
7
6
5
432
1
0
TSLIPM
0
EFTCM
0
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