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| 型號(hào)： | MCP6024-E/ST |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 13/42頁(yè) |
| 文件大小： | 0K |
| 描述： | IC OPAMP QUAD 2.5V 10MHZ 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 放大器類(lèi)型： | 通用 |
| 電路數(shù)： | 4 |
| 輸出類(lèi)型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 7 V/µs |
| 增益帶寬積： | 10MHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 1mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 679 (CN2011-ZH PDF) |
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MCP6021/1R/2/3/4
DS21685D-page 20
2009 Microchip Technology Inc.
4.9
PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012
Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/1R/2/3/4 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-11 shows an example of this type of layout.
FIGURE 4-11:
Example Guard Ring
Layout.
1.
Non-inverting Gain and Unity-Gain Buffer.
a)
Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b)
Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
2.
Inverting (Figure 4-11) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
a)
Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
b)
Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.10
High Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques will help you
achieve the performance shown in Section 1.0 “Elec-
formance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low speed from high
speed and low power from high power. This will reduce
interference.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
4.11
Typical Applications
4.11.1
A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
Figure 4-12 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a band-
width of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 dB attenuation at 60 kHz).
FIGURE 4-12:
A/D Converter Driver and
Anti-aliasing Filter with a 20 kHz Cutoff
Frequency.
This filter can easily be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
Guard Ring
VIN–VIN+
14.7 k
Ω 33.2 kΩ
1.0 nF
100 pF
MCP602X
8.45 k
Ω
1.2 nF
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