參數(shù)資料
型號： MCP4726A3T-E/CH
廠商： Microchip Technology
文件頁數(shù)： 35/86頁
文件大?。?/td> 0K
描述： IC DAC 12BIT NV EEP I2C SOT-23-6
標準包裝： 3,000
設(shè)置時間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 452mW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應商設(shè)備封裝： SOT-23-6
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
MCP4706/4716/4726
DS22272C-page 40
2011-2012 Microchip Technology Inc.
4.5
Power-Down Operation
To allow the application to conserve power when the
DAC operation is not required, three Power-Down
modes are available. The Power-Down Configuration
bits (PD1:PD0) control the power-down operation
(Figure 4-7). All Power-Down modes do the following:
Turn off most of its internal circuits (op amp, resis-
tor ladder, ...)
Op amp output becomes high-impedance to the
VOUT pin
Disconnects resistor ladder from reference
voltage (VRL)
Retains the value of the volatile DAC register and
Configuration bits, and the nonvolatile (EEPROM)
DAC register and Configuration bits
Depending on the selected Power-Down mode, the
following will occur:
VOUT pin is switched to one of three resistive pull-
downs (See Table 4-2)
- 640k
Ω (typical)
- 125k
Ω (typical)
-1k
Ω (typical)
There is a delay (TPDE) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op
amp no longer driving the VOUT output and the pull-
down resistors are sinking current.
In any of the Power-Down modes, where the VOUT pin
is not externally connected (sinking or sourcing
current), the power-down current will typically be 60 nA
the I2C commands for writing the power-down bits. The
commands that can update the volatile PD1:PD0 bits
are:
FIGURE 4-7:
Op Amp to VOUT Pin Block
Diagram.
4.5.1
EXITING POWER-DOWN
When the device exits the Power-Down mode, the
following occurs:
Disabled circuits (op amp, resistor ladder, ...) are
turned on
Resistor ladder is connected to selected
reference voltage (VRL)
Selected pull-down resistor is disconnected
The VOUT output will be driven to the voltage
represented by the volatile DAC register’s value
and Configuration bits
The VOUT output signal will require time as these
circuits are powered up and the output voltage is driven
to the specified value as determined by the volatile
DAC register and Configuration bits.
The following events will change the PD1:PD0 bits to
‘00’ and therefore exit the Power-Down mode. These
are:
Any I2C Write command for where the PD1:PD0
bits are ‘00’
(if nonvolatile PD1:PD0 bits are ‘00’)
Note:
The I2C serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
I2C master device.
TABLE 4-2:
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
PD1
PD0
Function
00
Normal operation
01
1k
Ω resistor to ground
10
125 k
Ω resistor to ground
11
640 k
Ω resistor to ground
Note:
Since the op amp and resistor ladder were
powered off (0V), the op amp’s input
voltage (VW) can be considered 0V. There
is a delay (TPDD) between the PD1:PD0
bits updated to ‘00’ and the op amp driving
the VOUT output. The op amp’s settling
time (from 0V) needs to be taken into
account to ensure the VOUT voltage
reflects the selected value.
VOUT
PD1:PD0
Op
Amp
1k
Ω
125
k
Ω
64
0
k
Ω
Gain (1x or 2x)
(Gx = 0 or 1)
VW
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